Super-compact universal quantum logic gates with inverse-designed elements

Integrated quantum photonic circuit is a promising platform for the realization of quantum information processing in the future. To achieve the large-scale quantum photonic circuits, the applied quantum logic gates should be as small as possible for the high-density integration on chips. Here, we report the implementation of super-compact universal quantum logic gates on silicon chips by the method of inverse design. In particular, the fabricated controlled-NOT gate and Hadamard gate are both nearly a vacuum wavelength, being the smallest optical quantum gates reported up to now. We further design the quantum circuit by cascading these fundamental gates to perform arbitrary quantum processing, where the corresponding size is about several orders smaller than that of previous quantum photonic circuits. Our study paves the way for the realization of large-scale quantum photonic chips with integrated sources and can have important applications in the field of quantum information processes.

. The quantum chip for measuring the CNOT gate. a. The microscope picture of the quantum chip, which corresponds to Fig. 1a in the main text. Because the microscope field of view is relatively small, the whole microscope picture is taken by twice independent photographing. And then we joint them together. b. The SEM image of the CNOT gate and its connected waveguide. c. The enlarged SEM image of the CNOT gate.

S2. The detailed optimization procedures of Hadamard and CNOT gates.
From the main text, it is known that the kernels of the Hadamard and CNOT gates are mainly formed by the 50:50 and 33:67 beam splitters for the linear optical scheme. Thus, in this section, we focus on the optimization of the 50:50 and 33:67 beam splitter in a single structure, where a pair of input ports and two output ports (named ain, bin and aout, bout ports) exist, as shown in Fig. S2a. Note that in our optimization process, the squares of the amplitude of the single photon quantum state corresponds to the optical field energy.
For the 50:50 beam splitter, if only one single photon is injected into the system from any input port (ain or bin), the output photonic quantum state could become the superposition at two output ports (aout and bout) with equal squares of amplitudes at the same time. To fulfill these operations, the system must possess a mirror symmetry with respect the dashed line (called mirror symmetry line), as marked in Fig. S2a. In this case, only a half region is needed to be optimized where the other mirror symmetric part should have the same dielectric distribution.

S3. The detailed discussion of the sensitivity analysis of the device performance.
In optical chip fabrication, the most common defect is the manufacturing deviation. Generally, there is an error of 20nm in the e-beam lithography etching, due to the instability of the dose of the electron beam. Thus, the designed device can be used for experimental fabrication if it can tolerate a manufacturing defect of under (over) etching with ±10nm.
Here, we consider the sensitivity analysis of the device performance with some manufacturing defects. Such an analysis includes two aspects: the first one is that we used the double filtering method (Refs. [45,46] in the main text) in the inverse-design process, which can increase the robustness of the device; the second one is that we also did a simulation to verify the performance of our device. Let us introduce them in detail: 1) In order to increase the robust property against manufacturing defects, we use the double filtering method in the inverse-design process. In brief, the double filtering method consists of applying the filter and threshold procedure twice on the design field, where in the second application three different threshold values are applied to obtain three different realizations of the design fields corresponding to under (over) etching. So, the over and under etching cases are simultaneously optimized. In such a way, we can get a robust device against the manufacturing defect of under (over) etching, which is the most common defect in optical chip fabrication. Thus, the inversedesigned structure possesses the robust property against manufacturing defects in a certain extent.
2) After getting the inverse-designed structure from the optimization process, we further verify the device performance against manufacturing defects by the simulation. Here, we get three structures from the optimization results, which are exact etching (0nm) case and over or under etching (±10nm) cases. As shown in Fig. S3a, we selected 33:67 beam splitter as an example to perform sensitivity analysis. In the enlarged view of Fig. S3b of the main text.

S4. The detailed discussion of the arbitrary single qubit gate.
The single qubit gate consists of the Hadamard gate and the phase z gate. To ensure that their quantum circuits cascaded by individual gates work well, we must consider that the operating frequency range of these designed devices can cover each other.
First, we study the operating frequency range of the phase z gate by the simulation. We fix L2=0.1μm and calculate the phase difference between the two waveguides after the gate by sweeping the parameter L1, as shown in Fig. S4. It can be seen that in the whole communication band (1500-1600nm), the phase z gate can generate a stable phase difference θ by adjusting L1. And then, we study the theoretical model and the numerical simulation of the arbitrary single qubit gate R, as mentioned in Fig. 2g When a quantum state in ϕ is injected into the single qubit gate R, any unitary transformation can be acted on it by adjusting the phase of θ1, θ2, and θ3. Now, we give three examples to demonstrate its function through the numerical simulations. In these three cases, the fixed phases in R gates are determined as θ1=π, θ2=π/2, and θ3=0, respectively. Hence, based on Eq. (S1), the output qubits a, b, and c become 0 , 1 ( 0 i 1 ) 2 + , and 1 , where 0 and 1 are the quantum state in the different paths. As shown in Figs. S5a-S5c, these three cases are simulated with the single photon exciting from the upper waveguide, where the quantum state is defined as 0 . Correspondingly, the quantum state in the lower waveguide is 1 . We find that the output quantum states indeed become the expected states after going through the R gate. In Fig. S5d, we mark these output quantum states to three points on the Bloch sphere. By the way, an arbitrary output quantum state can also be generated by the R gate, corresponding to the arbitrary point on the Bloch sphere. So, the simulation results possess a nice consistency with the theory results. It indicates that the R gate has a high performance even though that is integrated into such a small footprint. The overall size of the single-qubit quantum circuit in Fig. S5a-S5c is about 20μm×10μm. Finally, let us explain the reason for the ultra-compact footprint of the cascaded R gate. In previous works, the quantum circuits are constructed by optical devices with large footprints and some connected waveguides on chips. The length of the waveguides is on the same order of magnitude with the size of optical devices. Due to the fabrication error, the phase accumulative effect causes an unstable phase difference between these waveguides. Thus, an additional heat electrode is indispensable to correct the phase difference between the path-encoded waveguides.
The large optical devices and the connected waveguides with electrodes cover an enormous footprint with the scale of millimeters in traditional schemes. It brings about a great disadvantage for large-scale integrations. However, for our inverse-designed gate with a supercompact footprint (less than a wavelength), the length of the corresponding connected waveguide is about several micrometers. In this scale, the accumulative phase is so small that can be ignored. Thus, the R gate can be integrated into such a small area. Furthermore, the quantum circuits can be constructed by the R gates and the CNOT gates. In general, the size of quantum circuits can be effectively reduced from ~10 7 μm 2 in the previous work to ~10 3 μm 2 by using our inverse-designed quantum gates. The footprint is shrunk 4 orders of magnitude. The supercompact footprint of our devices indicates that more than 10 4 quantum circuits can be integrated into the same area. For modern fabrication technology of the photonic chip, such a 2-qubit circuit (Ref. [5] of the main text) can be implemented based on the basic logic components of Hadamard and CNOT gates.
S5. The imaginary parts for the density matrices of the bell states and the reconstructed process matrix of the CNOT gate.
To completely characterize the CNOT gate and its generated bell states, we plot the imaginary parts for the density matrices of the bell states and the reconstructed process matrix of the CNOT gate, as shown in Fig. S6. It is seen that these imaginary parts can be limited to very small values (close to zero). Thus, we believe our inverse-designed CNOT gate possess a high performance. (e) The imaginary part of the reconstructed process matrix of the CNOT gate.

S6. The overall size of the proposed quantum circuit.
Here, we also show the overall size of the design layout for our proposed inverse-designed quantum circuit in Fig. S7a. This corresponds to the theoretical model shown in Fig. S7b. The overall size of the quantum circuit in Fig. 4 of the main text is about 100μm×25μm.

S7. The simulation details of the optical transform matrix.
In Figs. 4b and 4d of the main text, we study the evolution process of the quantum state in the quantum circuit with the single photon exciting. The comparison figures of simulation and theory results are plotted in Figs. 4c and 4e of the main text. Next, we can also obtain the total optical matrix of the quantum circuit. Here, we mainly introduce the transform matrix method to obtain the theory results.
First, we build the transform matrices, M1, M2, and M3, of these optical devices. Their expressions are